GSSE SEMINAR by Prof. Ivo W. Rangelow on 24 November 2017



Speaker: Prof. Ivo W. Rangelow

Date: 24th of November, 2017

Time: 10.30 A.M.

Place: Student Council Room, Koç University Student Center, Floor 1

Self-sensing and Self-actuating Cantilever for

Field-Emission Scanning Probe Lithography (FE-SPL)



Ivo W. Rangelow, Claudia Lenk, Tzvetan Ivanov, Ahmad Ahmad, Steve Lenk, Elshad Guliyev, Martin Hofmann, Marcus Kaestner, Alexander Reumna, Mathias Holzna


Department of Micro- and Nanoelectronic Systems (MNES), Institute of Micro and Nanoelectronics,

Ilmenau University of Technology, Gustav-Kirchhoff-Str. 1, 98693 Ilmenau, Germany

naNano Analytik GmbH, Ehrenbergstraße 11, 98693 Ilmenau, Germany





The ability of rapid manufacturing of features in the sub-10-nm regime in a reproducible manner has been identified as one of the most important steps to enable future nanoelectronic, NEMS, photonic, and bio-nanotechnology-based devices. We elaborate on the efforts toward the downsizing of self-sensed and self-actuated probes as well as on upscaling by active cantilever arrays. We will present present the fabrication process of active probes along with the tip customizations carried out targeting specific application fields. As promising application in scope of nanofabrication, field emission scanning probe lithography is introduced. We discuss their control and design approach. Here, multilayer cantilevers and flexure piezo-scanners are combined in order to simultaneously meet both the range and speed requirements of a new generation of ultra-fast scanning probe microscopes.

We are presenting also low energy electron exposure emitted from a scanning proximal probe tip [1-5]. Here, the electron energy is close to lithographic relevant excitation and the electrons penetration volume is minimized. In consequence a much more spatially confined lithographic interaction is enabled. Based on the thermally actuated, piezoresistive cantilever technology we have developed a scanning probe lithography (SPL) platform able to image, inspect, align and pattern features down to single digit nano regime.

Herein, we present: (a) Closed loop lithography for generation of lithographic features in positive and negative tone; (b) Single digit (sub-10 nm) resolution and alignment capability; (c) Step-and-repeat, multi-step and multi-layer lithography; (d) Mix & Match Lithography capability for throughput enhancement; (e) Pattern transfer capability by using cryogenic plasma etching.

Within the talk the applied technology chain from basics towards application in terms of beyond CMOS device fabrication will be discussed.



[1] M. Kaestner, M. Hofer, I. W. Rangelow, J. Micro/Nanolith. MEMS MOEMS 12, 031111 (2013).

[2] M. Kaestner et al., J. Vac. Sci. Technol. B 32, 06F101 (2014).

[3] M. Kaestner et al., J. Micro/Nanolith. MEMS MOEMS 14, 031202 (2015).

[4] I. W. Rangelow et al., J. Vac. Sci. Technol. B 34, 06K202 (2016)

[5] I. W. Rangelow et al., J. Vac. Sci. Technol. B 35, 06G101 (2017)